Power Efficient Dual Edge-Triggered Storage Design
نویسندگان
چکیده
منابع مشابه
Multi-Threshold Based Low Power Dual Edge Triggered Flip-Flop
Digital circuit design is streamlined process used to improve the performance of a circuit for a particular application. Fast speed, minimum power dissipation and less area are the desirable characteristics of a digital circuit, in general. To meet a particular standard of speed, a compromise in power dissipation and speed is required. Timing elements such as Flip-flop are used as clock generat...
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Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timi...
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The normal D flipflop consumes very high power. So in this paper we enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 90nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to static output-controlled discharge Flip– Flop (SCDFF). SCDFF involves an explicit pulse generator and a latch that capture...
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In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed. Pulsetriggered flip-f...
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ژورنال
عنوان ژورنال: International Journal of Engineering and Technology
سال: 2017
ISSN: 2319-8613,0975-4024
DOI: 10.21817/ijet/2017/v9i2/170902323